This invention is in the field of preamplifier circuits for hard disk drives, and is more specifically directed to the mechanical interface for such preamplifiers.
Magnetic disk drive technology is the predominant mass non-volatile storage technology in modern personal computer systems, and continues to be an important storage technology for mass storage applications in other devices, such as portable digital audio players. As is fundamental in the field of magnetic disk drives, data is written by magnetizing a location (“domain”) of a layer of ferromagnetic material disposed at the surface of a disk platter. Each magnetized domain forms a magnetic dipole, with the stored data value corresponding to the orientation of that dipole. The “writing” of a data bit to a domain is typically accomplished by applying a current to a small electromagnet coil disposed physically near the magnetic disk, with the polarity of the current through the coil determining the orientation of the induced magnetic dipole, and thus the data state written to the disk. In modern disk drives, a magneto-resistive element is used to sense the orientation of the magnetic dipole at selected locations of the disk surface, thus reading the stored data state. Typically, the write coil and the magneto-resistive element are physically placed within a read/write “head”.
Data communication to and from the read/write heads in a modern disk drive system is carried out by way of a disk drive controller. Years ago, these disk drive controllers were generally implemented as a separate card within a computer system, given the substantial circuitry required to carry out such functions as mapping logical addresses to physical addresses, servo control of the spindle motor that rotates the disks and of the voice coil motor that positions the read/write heads at the desired location of the disk surface, and the like. Significant advances have been made in recent years both to greatly increase the density of data stored per unit area of the magnetic disk surface, and also to miniaturize the disk drive controller circuitry. Indeed, modern miniaturized hard disk drive systems, such as used in modern personal computers and notebook computers, and also as used in small-scale systems such as digital audio players, have placed the disk drive controller functionality at the disk drive itself, with some circuit functions even being moved out to the actuator arm.
A typical architecture of a conventional disk drive controller includes a processor or main controller circuit, for example implemented as a digital signal processor (DSP) or other programmable processor, along with the appropriate memory resources, for controlling the operation of the disk drive system, including such functions as address mapping, error correction coding and decoding, and the like. This controller is in bidirectional communication with a preamplifier function, which includes preamplifier circuitry for generating an electrical signal based on variations in the resistance of a magnetoresistive read heads, and which also includes write driver circuitry for generating write current applied to the inductive write heads. Other ancillary circuitry is also included in the preamplifier function, including circuitry for applying a DC bias to the magnetoresistive read head, fly height control circuitry for controllably heating the read/write head assemblies to maintain a constant fly height, as known in the art.
As such, data and control communication is required between the main controller and the preamplifier. FIG. 1 illustrates an example of a conventional architecture including controller 2 and preamplifier 4. In this example, preamplifier 4 includes amplifier 7, which is connected to magnetoresistive read head 3, and write driver 9, which is connected to inductive write head 5; these connections occupy four external terminals of preamplifier 4, as shown. Typically, conventional preamplifiers 4 communicate with multiple read/write heads in the disk drive system (e.g., as many as eight read/write heads), in which case multiple groups of external terminals will be provided, for example as illustrated for read/write circuitry 12 of preamplifier 4, serving another read/write head k. Three terminals of preamplifier 4 are also required for the power supply connections, in this case including the Vcc and Vee power supply voltages, and a ground connection, each of which are sourced through controller 2, as shown in FIG. 1. Various termination resistors are included within controller 2 and preamplifier 4, as conventional in the art and as shown in FIG. 1.
Preamplifier 4 includes conventional functions, such as data driver 11, data receiver 13, serial interface 10, and fault/buffered head voltage (BHV) circuit 8. Via a pair of external terminals, data driver 11 drives differential signal lines RDX, RDY that are connected to controller 2. Differential signal lines RDX, RDY communicate, to controller 2, data read from the disk drive via read head 3, amplifier 7, and other circuitry within preamplifier 4. Conversely, data receiver 13 receives a differential signal, at a pair of external terminals, from differential signal lines WDX, WDY, which are driven by controller 2. Differential signal lines WDX, WDY thus communicate, to preamplifier 4, data to be written to the disk drive via write head 5. Preamplifier 4 also receives at, an external terminal, a control signal from line R/xW indicating whether a read or a write operation is requested by controller 2. Head select and other control information is communicated by controller 2 over serial data line SDAT, serial clock line SCLK, and serial data enable line SDEN, to serial interface 10 of preamplifier 4. Fault/BHV circuitry 8 of preamplifier 4 issues fault signals, and also presents an analog signal indicative of the buffered head voltage (BHV) of a selected read head 3 when placed in a BHV sense mode by control information received by serial interface 10. These fault and BHV signals are communicated over signal line FLT&BHV, which occupies another external terminal of preamplifier 4.
FIGS. 2a and 2b illustrate the operation of controller 2 and preamplifier 4 in communicating with one another over the interface illustrated in FIG. 1, for this conventional architecture, over a sequence of operations. Between time t0 and time t1 of FIG. 2a, preamplifier 4 is in a “sleep”, or “idle”, state, in which no data is being written to or read from preamplifier 4 by controller 2. Just prior to time t1, controller 2 asserts serial data enable signal SDEN. During the active high level of this signal, controller 2 issues serial data to preamplifier 4 on serial data line SDAT, in combination with cycles of serial clock signal SCLK (not shown). It is contemplated that, given the serial nature of this communication, multiple data values will be communicated during the active duration of serial data line SDAT; such multiple data values are not specifically shown in FIG. 2a, for the sake of clarity. In this example, the serial data communicated in cycle n includes control data to cause preamplifier 4 to enter data read/write operations, with the direction of data indicated by the state of read/write signal line R/xW, and with other control information communicated over serial data line SDAT in cycle n. Controller 2 then de-asserts serial data enable signal line SDEN.
In the example illustrated in FIG. 2a, a read operation begins at time t1, because controller 2 has asserted signal line R/xW to an active high level, indicating a data read operation. During this read, differential data signals will be driven by preamplifier 4 onto lines RDX, RDY (not shown in FIG. 2a), for communication of data read via a selected read head 3, to controller 2. But, as shown in FIG. 1, because the data lines RDX, RDY are separate from the serial signal lines SDEN, SCLK, SDAT, serial communication between controller 2 and preamplifier 4 can be carried out simultaneously and in parallel with the communication of read data on lines RDX, RDY. This simultaneous serial communication is indicated in FIG. 2a by the dashed active periods on lines SDEN, SDAT between time t1 and time t2.
A data write operation then begins, as indicated by the high-to-low transition of signal line R/xW driven by controller 2 just prior to time t2. During this write operation, controller 2 will issue data on lines WDX, WDY, in the form of differential signals, corresponding to data to be written to the disk surface by the write head associated with the read head from which data was read in the previous operation, in this example. As in the read operation, serial data may be communicated simultaneously with the write data transfer to serial interface 10, over signal lines SCLK, SDEN, SDAT, as indicated by the dashed active periods on lines SDEN, SDAT shown in FIG. 2b. Near the end of this operation, prior to time t3 in this example, this serial communication includes the selection of a different read/write head for the next operation, along with other control information, as evident from the active period shown for serial data enable line SDEN and the serial data information on line SDAT illustrated in FIG. 2b, both driven by controller 2; as before, serial clock line SCLK is driven by controller 2 with a clock signal that synchronizes the serial data transfer into serial interface 10. In this example, this control information can include selection of a different read head from that in the previous operation. Also at about time t3, controller 2 asserts signal line R/xW to a high active level, indicating that the next operation is a data read.
Following time t3, and during the data read operation, controller 2 initiates control information that will place preamplifier 4 into an idle state, because of the absence of data to be written or disk locations to be read, and to save power. This is accomplished by controller 2 asserting serial data enable line SDEN in combination with source serial control data requesting the idle operation on line SDAT and corresponding cycles of serial clock SCLK (not shown). Upon completion of this serial communication, at time t4, preamplifier 4 enters the idle mode again.
FIG. 2b illustrates the operation of preamplifier 4 and controller 2 in an example of operation in which preamplifier 4 issues a fault signal to controller 2. In this example, the fault is detected by preamplifier 4 after time t3, during the read operation, with preamplifier 4 driving line FLT&BHV to an active high level. In response to this fault signal, controller 2 issues a high active signal on line SDEN, and serially communicates control information to preamplifier 4 on serial data line SDAT, with the control information including such information useful in clearing or investigating the reason for the fault signal, and also control information responding to the fault.
As evident from FIG. 1, conventional preamplifier 4 requires twelve external terminals beyond those required for communicating with the read/write heads. While the number of terminals for communication with read/write heads will tend to dominate the pinout of preamplifier 4, the physical interface between preamplifier 4 and controller 2 is highly constrained in modern small form factor hard disk drives, especially considering the width of conductors required to run to preamplifier 4 for power supply voltages Vcc, Vee, and ground.
By way of further background, U.S. Patent Application Publication No. US 2006/0193071 A1, entitled “HIDID Preamp-to-Host Interface with Much Reduced I/O Lines”, commonly assigned with this application and incorporated herein by reference, describes an approach to combining the functions of the terminals for the signal lines between a preamplifier and a controller in a disk drive system. According to this publication, two terminals are used for the read signals (RDX, RDY), write signals (WDX, WDY), and also for the serial communication (SCLK, SDAT), depending on the mode selected.